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s 6b 0796 240 seg / com driver for stn lcd january, 2000 ver. 1.0 prepared by: gyeong-nam, kim kgn@samsung.co.kr contents in this document are subject to change without notice. no part of this document may be reproduced or transmitted in any form or by any means, electronic or mechanical, for any purpose, without the express written permission of lcd driver ic team.
240 seg / com driver for stn lcd preliminary spec. ver. 1.0 s 6b 0796 2 S6B0796 specification revision history version content date 0.0 l original jun e .1999 0.1 l p6 , p16 revision august .1999 1.0 l p4 introduction revision. january. 2000
s 6b 0796 preliminary spec. ver. 1.0 240 seg / com driver for stn lcd 3 contents introduction ................................ ................................ ................................ ................................ .................. 4 features ................................ ................................ ................................ ................................ .......................... 4 block diagram ................................ ................................ ................................ ................................ ............... 5 pad configuration (tbd) ................................ ................................ ................................ ............................. 6 pad center coordinates ................................ ................................ ................................ ............................ 7 pin description ................................ ................................ ................................ ................................ .............. 9 functional description ................................ ................................ ................................ ............................ 10 block function ................................ ................................ ................................ ................................ ..... 10 pin function ................................ ................................ ................................ ................................ ........... 11 functional operations ................................ ................................ ................................ ...................... 15 specifications ................................ ................................ ................................ ................................ .............. 18 absolute maximum ratings ................................ ................................ ................................ ............... 18 recommended operating conditions ................................ ................................ ........................... 18 dc characteristics ................................ ................................ ................................ ............................. 19 ac characteristics ................................ ................................ ................................ ............................. 21 precaution ................................ ................................ ................................ ................................ .................... 28 connection examples of plural segment drivers ................................ ................................ ........ 29 timing chart of 4-device casecade connection of segment drivers ................................ ...... 30 connection examples of plural common drivers ................................ ................................ ......... 31
240 seg / com driver for stn lcd preliminary spec. ver. 1.0 s 6b 0796 4 introduction the S6B0796 is a 240-outputs segment/common driver lsi for graphic dot-matrix liquid c rystal display systems. it is fabricated by low power cmos high voltage process technology. this device consists of 240-bits bi-directional shift register, 240-bits data latch and 240-bits driver. in case of segment mode, the data input is selected 4bit parallel input mode and 8bit parallel input mode by a mode (md) pin. in case of common mode, data input/output pins are bi-directional , four data shift directions are pin-selectable . features both seg ment m ode and c ommon m ode - supply voltage for lc driver: +15.0 to +32.0v - number of lc driver outputs: 240 - low output impedance - low power consumption - supply voltage for the logic system: +2.4v to +5.5v - cmos silicon gate process (p-type silicon substrate) - package: 268-pin tcp (tape carrier package) or gold bump ed chip segment m ode - shift clock frequency: 20mhz (max) (vdd=+5v 10%) 12mhz (max) (vdd=+2.4v to +4.5v) - adopts a data bus system - 4- / 8-bit parallel input modes are selectable with a mode (md) pin - automatic transfer function of an enable signal - automatic counting function which, in the chip select, causes the internal clock to be stopped by automatically counting 240 of input data - line latch circuit reset function when dispoffb active common m ode - shift clock frequency: 4.0mhz (max) (vdd=+2.4v to +5.5v) - built-in 240-bits bi-directional shift register (divisible into 120-bits 2) - available in a single mode (240-bits shift register) or in a dual mode (120-bits shift register 2) - shift register circuit reset function when dispoffb active
s 6b 0796 preliminary spec. ver. 1.0 240 seg / com driver for stn lcd 5 block diagram level shifter 240 bits 4-level driver 240 bits level shifter 240 bits line latch/shifter register data latch control sp conversion & data control (4 to 8 or 8to 8) active control 260 257 259 247 control logic 258 256 261 262 246 268 267 266 265 1 2 240 239 244 243 242 241 248 249 250 251 252 253 254 255 264 245 8bits*2 data latch fr dispoffb eio1 eio2 lp xck l/r md s/c d i 0 d i 1 d i 2 d i 3 di 4 di 5 di 6 di 7 v dd v ss v 5l v 43l v 12l v ol y 240 y 239 y 1 y 2 v or v 12r v 43r v 5l 240 240 16 16 16 16 16 16 16 8 16 figure 1 . block diagram
240 seg / com driver for stn lcd preliminary spec. ver. 1.0 s 6b 0796 6 pad configuration eeeeeeeeeeeeeeeeeeeee - - - - - - - - - - eeeeeeeeeeeeeeeeeeee y 1 240 292 241 289 244 s 6b 0796 (top view , pads up ) (0,0) x e e e e e e e e e e e e e e - - - - - - - - - - e e e e e e e e e e e e e e e e e e e e e 288 245 figure 2 . S6B0796 chip configuration table 1 . S6B0796 pad dimensions size item pad no. x y unit chip size - 16200 1100 pad pitch 1 to 240 241 to 292 65 (min.) 260 (min.) 1 to 240 43 108 241 to 244 289 to 292 76 73 bumped pad size 245 to 288 58 76 bumped pad height 1 to 292 14 ( typ.) m m
s 6b 0796 preliminary spec. ver. 1.0 240 seg / com driver for stn lcd 7 pad center coordinates table 2 . pad center coordinates [unit: m m] no name x y no name x y no name x y 1 y1 7767.5 395 51 y51 4517.5 395 101 y101 1267.5 395 2 y2 7702.5 395 52 y52 4452.5 395 102 y102 1202.5 395 3 y3 7637.5 395 53 y53 4387.5 395 103 y103 1137.5 395 4 y4 7572.5 395 54 y54 4322.5 395 104 y104 1072.5 395 5 y5 7507.5 395 55 y55 4257.5 395 105 y105 1007.5 395 6 y6 7442.5 395 56 y56 4192.5 395 106 y106 942.5 395 7 y7 7377.5 395 57 y57 4127.5 395 107 y107 877.5 395 8 y8 7312.5 395 58 y58 4062.5 395 108 y108 812.5 395 9 y9 7247.5 395 59 y59 3997.5 395 109 y109 747.5 395 10 y10 7182.5 395 60 y60 3932.5 395 110 y110 682.5 395 11 y11 7117.5 395 61 y61 3867.5 395 111 y111 617.5 395 12 y12 7052.5 395 62 y62 3802.5 395 112 y112 552.5 395 13 y13 6987.5 395 63 y63 3737.5 395 113 y113 487.5 395 14 y14 6922.5 395 64 y64 3672.5 395 114 y114 422.5 395 15 y15 6857.5 395 65 y65 3607.5 395 115 y115 357.5 395 16 y16 6792.5 395 66 y66 3542.5 395 116 y116 292.5 395 17 y17 6727.5 395 67 y67 3477.5 395 117 y117 227.5 395 18 y18 6662.5 395 68 y68 3412.5 395 118 y118 162.5 395 19 y19 6597.5 395 69 y69 3347.5 395 119 y119 97.5 395 20 y20 6532.5 395 70 y70 3282.5 395 120 y120 32.5 395 21 y21 6467.5 395 71 y71 3217.5 395 121 y121 -32.5 395 22 y22 6402.5 395 72 y72 3152.5 395 122 y122 -97.5 395 23 y23 6337.5 395 73 y73 3087.5 395 123 y123 -162.5 395 24 y24 6272.5 395 74 y74 3022.5 395 124 y124 -227.5 395 25 y25 6207.5 395 75 y75 2957.5 395 125 y125 -292.5 395 26 y26 6142.5 395 76 y76 2892.5 395 126 y126 -357.5 395 27 y27 6077.5 395 77 y77 2827.5 395 127 y127 -422.5 395 28 y28 6012.5 395 78 y78 2762.5 395 128 y128 -487.5 395 29 y29 5947.5 395 79 y79 2697.5 395 129 y129 -552.5 395 30 y30 5882.5 395 80 y80 2632.5 395 130 y130 -617.5 395 31 y31 5817.5 395 81 y81 2567.5 395 131 y131 -682.5 395 32 y32 5752.5 395 82 y82 2502.5 395 132 y132 -747.5 395 33 y33 5687.5 395 83 y83 2437.5 395 133 y133 -812.5 395 34 y34 5622.5 395 84 y84 2372.5 395 134 y134 -877.5 395 35 y35 5557.5 395 85 y85 2307.5 395 135 y135 -942.5 395 36 y36 5492.5 395 86 y86 2242.5 395 136 y136 -1007.5 395 37 y37 5427.5 395 87 y87 2177.5 395 137 y137 -1072.5 395 38 y38 5362.5 395 88 y88 2112.5 395 138 y138 -1137.5 395 39 y39 5297.5 395 89 y89 2047.5 395 139 y139 -1202.5 395 40 y40 5232.5 395 90 y90 1982.5 395 140 y140 -1267.5 395 41 y41 5167.5 395 91 y91 1917.5 395 141 y141 -1332.5 395 42 y42 5102.5 395 92 y92 1852.5 395 142 y142 -1397.5 395 43 y43 5037.5 395 93 y93 1787.5 395 143 y143 -1462.5 395 44 y44 4972.5 395 94 y94 1722.5 395 144 y144 -1527.5 395 45 y45 4907.5 395 95 y95 1657.5 395 145 y145 -1592.5 395 46 y46 4842.5 395 96 y96 1592.5 395 146 y146 -1657.5 395 47 y47 4777.5 395 97 y97 1527.5 395 147 y147 -1722.5 395 48 y48 4712.5 395 98 y98 1462.5 395 148 y148 -1787.5 395 49 y49 4647.5 395 99 y99 1397.5 395 149 y149 -1852.5 395 50 y50 4582.5 395 100 y100 1332.5 395 150 y150 -1917.5 395
240 seg / com driver for stn lcd preliminary spec. ver. 1.0 s 6b 0796 8 table 2. pad center coordinates (continued) [unit: m m] no name x y no name x y no name x y 151 y151 -1982.5 395 201 y201 -5232.5 395 251 dummy -5900 -419 152 y152 -2047.5 395 202 y202 -5297.5 395 252 vdd -5640 -419 153 y153 -2112.5 395 203 y203 -5362.5 395 253 vdd -5380 -419 154 y154 -2177.5 395 204 y204 -5427.5 395 254 vdd -5120 -419 155 y155 -2242.5 395 205 y205 -5492.5 395 255 vdd -4860 -419 156 y156 -2307.5 395 206 y206 -5557.5 395 256 vdd -4600 -419 157 y157 -2372.5 395 207 y207 -5622.5 395 257 sc -4340 -419 158 y158 -2437.5 395 208 y208 -5687.5 395 258 eio2 -4080 -419 159 y159 -2502.5 395 209 y209 -5752.5 395 259 di0 -3820 -419 160 y160 -2567.5 395 210 y210 -5817.5 395 260 di1 -3560 -419 161 y161 -2632.5 395 211 y211 -5882.5 395 261 di2 -3300 -419 162 y162 -2697.5 395 212 y212 -5947.5 395 262 di3 -3040 -419 163 y163 -2762.5 395 213 y213 -6012.5 395 263 di4 -2780 -419 164 y164 -2827.5 395 214 y214 -6077.5 395 264 di5 -2520 -419 165 y165 -2892.5 395 215 y215 -6142.5 395 265 di6 -2260 -419 166 y166 -2957.5 395 216 y216 -6207.5 395 266 di7 -2000 -419 167 y167 -3022.5 395 217 y217 -6272.5 395 267 xck 1770 -419 168 y168 -3087.5 395 218 y218 -6337.5 395 268 dispoffb 2030 -419 169 y169 -3152.5 395 219 y219 -6402.5 395 269 lp 2290 -419 170 y170 -3217.5 395 220 y220 -6467.5 395 270 eio1 2550 -419 171 y171 -3282.5 395 221 y221 -6532.5 395 271 fr 2810 -419 172 y172 -3347.5 395 222 y222 -6597.5 395 272 lr 3070 -419 173 y173 -3412.5 395 223 y223 -6662.5 395 273 md 3330 -419 174 y174 -3477.5 395 224 y224 -6727.5 395 274 nc 3590 -419 175 y175 -3542.5 395 225 y225 -6792.5 395 275 vss 3850 -419 176 y176 -3607.5 395 226 y226 -6857.5 395 276 vss 4110 -419 177 y177 -3672.5 395 227 y227 -6922.5 395 277 vss 4370 -419 178 y178 -3737.5 395 228 y228 -6987.5 395 278 vss 4630 -419 179 y179 -3802.5 395 229 y229 -7052.5 395 279 vss 4890 -419 180 y180 -3867.5 395 230 y230 -7117.5 395 280 vss 5150 -419 181 y181 -3932.5 395 231 y231 -7182.5 395 281 dummy 5410 -419 182 y182 -3997.5 395 232 y232 -7247.5 395 282 dummy 5670 -419 183 y183 -4062.5 395 233 y233 -7312.5 395 283 dummy 5930 -419 184 y184 -4127.5 395 234 y234 -7377.5 395 284 dummy 6190 -419 185 y185 -4192.5 395 235 y235 -7442.5 395 285 dummy 6450 -419 186 y186 -4257.5 395 236 y236 -7507.5 395 286 dummy 6710 -419 187 y187 -4322.5 395 237 y237 -7572.5 395 287 dummy 6970 -419 188 y188 -4387.5 395 238 y238 -7637.5 395 288 dummy 7230 -419 189 y189 -4452.5 395 239 y239 -7702.5 395 289 v5r 7969 -348.5 190 y190 -4517.5 395 240 y240 -7767.5 395 290 v43r 7969 -127.5 191 y191 -4582.5 395 241 v0l -7969 344.5 291 v12r 7969 93.5 192 y192 -4647.5 395 242 v12l -7969 93.5 292 v0r 7969 344.5 193 y193 -4712.5 395 243 v43l -7969 -127.5 194 y194 -4777.5 395 244 v5l -7969 -348.5 195 y195 -4842.5 395 245 dummy -7460 -419 196 y196 -4907.5 395 246 dummy -7200 -419 197 y197 -4972.5 395 247 dummy -6940 -419 198 y198 -5037.5 395 248 dummy -6680 -419 199 y199 -5102.5 395 249 dummy -6420 -419 200 y200 -5167.5 395 250 dummy -6160 -419
s 6b 0796 preliminary spec. ver. 1.0 240 seg / com driver for stn lcd 9 pin description pin no. symbol i/o description 1 to 240 y 1 ? y 240 o lc driver output 241, 292 v 0l , v 0r - power supply for lc driver 242, 291 v 12l , v 12r - power supply for lc driver 243, 290 v 43l , v 43r - power supply for lc driver 244, 289 v 5l , v 5r - power supply for lc driver 272 l/r i display data shift direction selection 252 to 256 v dd - power supply for logic system(+2.4 to +5.5v) 257 s/c i segment mode/common mode selection 258 eio 2 i/o input/output for chip select or data of shift register 259 to 265 di 0 ? di 6 i display data input for segment mode 266 di 7 i display data input for segment mode/dual mode data input 267 xck i display data shift clock input for segment mode 268 dispoffb i control input for deselect output level 269 lp i latch pulse input/shift clock input for shift register 270 eio 1 i/o input/output for chip select or data of shift register 271 fr i ac-converting signal input for lc driver waveform 273 md i mode selection input 275 to 280 v ss - ground(0v) table 3 pin description
240 seg / com driver for stn lcd preliminary spec. ver. 1.0 s 6b 0796 10 functional description block function . active control in case of segment mode, controls the selection or deselection of the chip. following a lp signal, and after the chip select signal is input, a select signal is generated internally until 240 bits of data have been read in. once data input has been completed, a select signal for cascade connection is output, and the chip is deselected. in case of common mode, controls the input/output data of bidirectional pins. . sp conversion & data control in case of segment mode, keep input data which are 2 clocks of xck at 4-bit parallel mode into latch circuit, or keep input data which are 1 clock of xck at 8-bits parallel mode into latch circuit, after that they are put on the internal data bus 8 bits at a time. . data latch control in case of segment mode, selects the state of the data latch which reads in the data bus signals. the shift direction is controlled by the control logic, for every 16 bits of data read in, the selection signal shifts one bit based on the state of the control circuit. . data latch in case of segment mode, latches the data on the data bus. the latched state of each lc driver output pin is controlled by the control logic and the data latch control, 240 bits of data are read in 30 sets of 8 bits. . line latch / shift register in case of segment mode, all 240 bits which have been read into the data latch are simultaneously latched on the falling edge of the lp signal, and output to the level shifter block. in case of common mode, shifts data from the data input pin on the falling edge of the lp signal. . level shifter the logic voltage signal is level-shifted to the lc driver voltage level, and output to the driver block. . 4-level driver driver the lc driver output pins from the line latch/shift register data, selecting one of 4 levels (v 0 , v 12 , v 43, v 5 ) based on the s/c, fr and dispoffb signals. . control logic controls the operation of each block. in case of segment mode, when a lp signal has been input, all blocks are reset and the control logic waits for the selection signal output from the active control block. once the selection signal has been output, operation of the data latch and data transmission are controlled, 240 bits of data are read in, and the chip is deselected. in case of common mode, controls the direction of data shift.
s 6b 0796 preliminary spec. ver. 1.0 240 seg / com driver for stn lcd 11 pin function segment mode symbol function v dd logic system power supply pin connects to +2.4 to +5.5v v ss ground pin connects to 0 v v 0r , v 0l v 12r , v 12l v 43r , v 43l v 5r , v 5l power supply pin for lc driver voltage bias. . normally, the bias voltage used is set by a resistor divider. . ensure that voltage are set such that v ss v 5 < v 43 < v 12 < v 0 . . to further reduce the difference between the output waveforms of lc driver output pins y 1 and y 160 , externally connect v ir and v il (i = 0, 12, 43, 5) di 0 ? di 7 input pin for display data . in 4-bit parallel input mode, input data into the 4 pins di 0 ? di 3 . connect di 4 ? di 7 to v ss or v dd . . in 8-bit parallel input mode, input data into the 8 pins di 0 ? di 7 . xck clock input pin for taking display data . data is read on the falling edge of the clock pulse. lp latch pulse input pin for display data . data is latched on the falling edge of the clock pulse. l/r direction selection pin for reading display data . when set to v ss level ?l?, data is read sequentially from y 240 to y 1 . . when set to v dd level h?, data is read sequentially from y 1 to y 240 . dispoffb control input pin for output deselect level . the input signal is level-shifted from logic voltage level to lc drive voltage level, and controls lc drive circuit. . when set to v ss level ?l?, the lc drive output pins (y 1 - y 240 ) are set to level v 5 . . while set to ?l?, the contents of the line latch are reset, but read the display data in the data latch regardless of condition of dispoffb. when the dispoffb function is canceled, the driver outputs deselect level (v 12 or v 43 ), then outputs the contents of the data latch on the next. falling edge of the lp. that time, if dispoffb removal time can not keep regulation what is shown ac characteristics (page 21 ), can not output the reading data correctly.
240 seg / com driver for stn lcd preliminary spec. ver. 1.0 s 6b 0796 12 fr ac signal input for lc driving waveform . the input signal is level-shifted from logic voltage level to lc drive voltage level, and controls lc drive circuit. . normally, inputs a frame inversion signal. . the lc driver output pin?s output voltage level can be set using the line latch output signal and the fr signal. table of truth values is shown in table 4. md mode selection pin . when set to v ss level ?l?, 8-bit parallel input mode is set. . when set to v dd level ?h?, 4-bit parallel input mode is set. . the relationship between the display data and driver output pins is shown in table 5. s/c segment mode/common mode selection pin . when set to v dd level ?h?, segment mode is set. eio 1 eio 2 input / output pin for chip selection . when l/r input is at v ss level ?l?, eio 1 is set for output, and eio 2 is set for input. . when l/r input is at v dd level ?h?, eio 1 is set for input, and eio 2 is set for output. . during output. set to ?h? while lp*xclkb is ?h? and after 240-bits of data have been read, set to ?l? for one cycle (from falling edge to falling edge of xck), after which it returns to ?h?. . during input, after the lp signal is input, the chip is selected while ei is set to ?l?. after 240-bits of data have been read, the chip is deselected. y 1 ? y 240 lc driver output pins . corresponding directly to each bit of the data latch, one level(v 0 , v 12 , v 43 , or v 5 ) is selected and output. table of truth values is shown in table 4.
s 6b 0796 preliminary spec. ver. 1.0 240 seg / com driver for stn lcd 13 common m ode symbol function v dd logic system power supply pin connects to +2.4 to +5.5v v ss ground pin connects to 0 v v 0r , v 0l v 12r , v 12l v 43r , v 43l v 5r , v 5l power supply pin for lc driver voltage bias. . normally, the bias voltage used is set by a resistor divider. . ensure that voltage are set such that v ss 240 seg / com driver for stn lcd preliminary spec. ver. 1.0 s 6b 0796 14 dispoffb control input pin for output deselect level . the input signal is level-shifted from logic voltage level to lc drive voltage level, and controls lc drive circuit. . when set to v ss level ?l?, the lc drive output pins(y 1 -y 240 ) are set to level v 5 . . while set to ?l?, the contents of the shift resister are reset not reading data. when the dispoffb function is canceled, the driver outputs deselect level(v 12 or v 43 ), and the shift data is reading on the falling edge of the lp. that time, if dispoffb removal time can not keep regulation what is shown ac characteristics (page 26), the shift data is not reading correctly. fr ac signal input for lc driving waveform . the input signal is level-shifted from logic voltage level to lc drive voltage level, and controls lc drive circuit. . normally, input a frame inversion signal. . the lc driver output pin?s output voltage level can be set using the shift register output signal and the fr signal. table of truth values is shown in table 4. md mode selection pin . when set to v ss level ?l?, single mode operation is selected, when set to v dd level ?h?, dual mode operation is selected. di 7 dual mode data input pin . according to the data shift direction of the data shift register, data can be input starting from the 121 st bit. when the chip is used as dual mode, di 7 will be pull-down. when the chip is used as single mode, di 7 won?t be pull-down. s/c segment mode/common mode selection pin . when set to v ss level ?l?, common mode is set. di 0 ? di 6 not used . connect di 0 ? di 6 to v ss or v dd . avoiding floating. xck not used . xck is pull-down in common mode, so connect to v ss or open. y 1 ? y 240 lc driver output pins . corresponding directly to each bit of the shift register, one level(v 0 , v 12 , v 43 , or v 5 ) is selected and output. table of truth values is shown in table 4.
s 6b 0796 preliminary spec. ver. 1.0 240 seg / com driver for stn lcd 15 functional operations t ruth table ( table 4 ) segment m ode fr latch data dispoffb driver output voltage level (y 1 ? y 240 ) l l h v 43 l h h v 5 h l h v 12 h h h v 0 x x l v 5 here, v ss v 5 < v 43 < v 12 < v 0 , h : v dd (+2.4v to +5.5v), l : v ss (0v), x : don?t care common m ode fr latch data dispoffb driver output voltage level (y 1 ? y 240 ) l l h v 43 l h h v 0 h l h v 12 h h h v 5 x x l v 5 here, v ss v 5 < v 43 < v 12 < v 0 , h : v dd (+2.4v to +5.5v), l : v ss (0v), x : don?t care note : there are two kinds of power supply (logic level voltage, lc drive voltage) for lcd driver, please supply regular voltage which assigned by specification for each power pin. that time ?don?t care? should be fixed to ?h? or ?l ?, avoiding floating.
240 seg / com driver for stn lcd preliminary spec. ver. 1.0 s 6b 0796 16 relationship between the display data and driver output pins ( table 5 ) segment m ode (a) 4-bit p arallel m ode figure of clock md l/r eio 1 eio 2 data input 1st 2nd 3 rd .. 58th 59th 60th di 0 y237 y233 y229 .. y9 y5 y1 di 1 y238 y234 y230 .. y10 y6 y2 di 2 y239 y235 y231 .. y11 y7 y3 h l output input di 3 y240 y236 y232 .. y12 y8 y4 di 0 y4 y8 y12 .. y232 y236 y240 di 1 y3 y7 y11 .. y231 y235 y239 di 2 y2 y6 y10 .. y230 y234 y238 h h input output di 3 y1 y5 y9 .. y229 y233 y237 (a) 8-bit p arallel m ode figure of clock md l/r eio1 eio2 data input 1st 2nd 3 rd .. 28th 29th 30th di 0 y233 y225 y217 .. y17 y9 y1 di 1 y234 y226 y218 .. y18 y10 y2 di 2 y235 y227 y219 .. y19 y11 y3 di 3 y236 y228 y220 .. y20 y12 y4 di 4 y237 y229 y221 .. y21 y13 y5 di 5 y238 y230 y222 .. y22 y14 y6 di 6 y239 y231 y223 .. y23 y15 y7 l l output input di 7 y240 y232 y224 .. y24 y16 y8 di 0 y8 y16 y24 .. y224 y232 y240 di 1 y7 y15 y23 .. y223 y231 y239 di 2 y6 y14 y22 .. y222 y230 y238 di 3 y5 y13 y21 .. y221 y229 y237 di 4 y4 y12 y20 .. y220 y228 y236 di 5 y3 y11 y19 .. y219 y227 y235 di 6 y2 y10 y18 .. y218 y226 y234 l h input output di 7 y1 y9 y17 .. y217 y225 y233
s 6b 0796 preliminary spec. ver. 1.0 240 seg / com driver for stn lcd 17 table 5 (continued) common m ode md l/r data transfer direction eio1 eio2 di7 l(shift to left) y 240 ? y 1 output input x l (single) h(shift to right) y 1 ? y 240 input output x h (dual) l(shift to left) y 240 ? y 121 y 120 ? y 1 output input input h(shift to right) y 1 ? y 120 y 121 ? y 240 input output input here, l : v ss (0v), h : v dd (+2.4v to +5.5v), x : don?t care note: ?don?t care? should be fixed to ?h? or ?l?, avoid floating.
240 seg / com driver for stn lcd preliminary spec. ver. 1.0 s 6b 0796 18 specifications absolute maximum ratings table 6. absolute maximum ratings parameter symbol conditions applicable pins ratings unit supply voltage (1) v dd ta=25 c referenced to v ss (0v) v dd -0.3 to +6.5 v v 0 v 0l, v 0r -0.3 to +35 v v 12 v 12l, v 12r -0.3 to v 0 +0.3 v v 43 v 43l, v 43r -0.3 to v 0 +0.3 v supply voltage (2) v 5 v 5l, v 5r -0.3 to v 0 +0.3 v input voltage v 1 di 0 ?di 7 , xck, lp, l/r, md, s/c, eio 1 , eio 2 , dispoffb -0.3 to v dd +0.3 v storage temperature t stg -45 to 125 c recommended operating conditions table 7. recommended operating conditions parameter symbol conditions applicable pins min. typ. max. unit supply voltage (1) v dd referenced to v ss (0v) v dd +2.4 +5.5 v supply voltage (2) v 0 v 0l, v 0r +15 +32 v operating temperature t opr -20 +85 c note: ensure that voltage are set such that v ss v 5 < v 43 < v 12 < v 0
s 6b 0796 preliminary spec. ver. 1.0 240 seg / com driver for stn lcd 19 dc characteristics dc characteristics(table 8) segment m ode (v ss =v 5 =0v, v dd =+2.4 to 5.5v, v 0 =+15 to +32v, ta=-20~85 c) parameter symbol conditions applicable pins min. typ. max. unit v ih 0.8v dd v input voltage v il di 0 -di 7 , xck, lp, l/r, fr, md, s/c,eio 1 , eio 2 , dispoffb 0.2v dd v v oh i oh =-0.4ma v dd -0.4 v output voltage v ol i ol =+0.4ma eio 1 , eio 2 +0.4 v i lih v i =v dd +10 ua input leakage current i lil v i =v ss di 0 -di 7 , xck, lp, l/r, fr, md, s/c,eio 1 , eio 2 , dispoffb -10 ua v 0 =+30v 1.5 2.0 k w output resistance r on | d v on | =0.5v v 0 =+20v y 1 - y 240 2.0 2.5 stand-by current i stb *1 v ss 75.0 ua consumed current(1) ( deselection) i dd1 *2 v dd 2.0 ma consumed current(2) (selection) i dd2 *3 v dd 12.0 ma consumed current i 0 *4 v 0 1.5 ma notes: *1 v dd =+5v, v 0 =+32v, v i =v ss *2 v dd =+5v, v 0 =+32v, f xck =20mhz, no-load, ei=v dd the input data is turned over by data taking clock (4-bit parallel input mode) *3 v dd =+5v, v 0 =+32v, f xck =20mhz, no-load, ei=v ss the input data is turned over by data taking clock (4-bit parallel input mode) *4 v dd =+5v, v 0 =+32v, f xck =20mhz, f lp =25.6 khz, f fr =80hz, no-load the input data is turned over by data taking clock (4-bit parallel input mode)
240 seg / com driver for stn lcd preliminary spec. ver. 1.0 s 6b 0796 20 table 8 (continued) common m ode (v ss =v 5 =0v, v dd =+2.4 to 5.5v, v 0 =+15 to +32v, ta=-20~85 c) parameter symbol conditions applicable pins min. typ. max. unit v ih 0.8v dd v input voltage v il di 0 -di 7 , xck, lp, l/r, fr, md, s/c,eio 1 , eio 2 , dispoffb 0.2v dd v v oh i oh =-0.4ma v dd -0.4 v output voltage v ol i ol =+0.4ma eio 1 , eio 2 +0.4 v i lih v i =v dd di 0 ?di 6 , lp, l/r, fr, md, s/c, dispoffb +10 ua input leakage current i lil v i =v ss di 0 -di 7 , xck, lp, l/r, fr, md, s/c,eio 1 , eio 2 , dispoffb -10 ua v 0 =+30v 1.5 2.0 k w output resistance r on | d on | =0.5v v 0 =+20v y 1 ? y 2 4 0 2.0 2.5 input pull- down current i pd v i =v dd xck, eio 1 , eio 2 , di 7 100.0 ua stand-by current i stb *1 v ss 75.0 ua consumed current(1) i dd *2 v dd 120.0 ua consumed current(2) i 0 *2 v 0 240.0 ua notes: *1 v dd =+5v, v 0 =+32v, v i =v ss *2 v dd =+5v, v 0 =+32v, f lp =25.6khz, f fr =80hz case of 1/320 duty operation, no-load
s 6b 0796 preliminary spec. ver. 1.0 240 seg / com driver for stn lcd 21 ac characteristics segment mode ac charac teristics (table 9) segment m ode 1 (v ss =v 5 =0v, v dd =+4.5 to +5.5v, v 0 =+15 to +32v, ta=-20~85 c) parameter symbol conditions min. typ. max. unit shift clock period *1 t wck t r , t f 10 ns 50 ns shift clock ?h? pulse width t wckh 15 ns shift clock ?l? pulse width t wckl 15 ns data setup time t ds 10 ns data hold time t dh 12 ns latch pulse ?h? pulse width t wlph 15 ns shift clock rise to latch pulse rise time t ld 0 ns shift clock fall to latch pulse fall time t sl 30 ns latch pulse rise to shift clock rise time t ls 25 ns latch pulse fall to shift clock fall time t lh 25 ns input signal rise time *2 t r 50 ns input signal fall time *2 t f 50 ns enable setup time t s 10 ns dispoffb removal time t sd 100 ns dispoffb ?l? pulse width t wdl 1.2 us output delay time (1) t d c l =15pf 30 ns output delay time (2) t pd1, t pd2 c l =15pf 1.2 us output delay time (3) t pd3 c l =15pf 1.2 us notes: *1 take the cascade connection into consideration. *2 (t wck ? t wckh ? t wckl ) / 2 is maximum in the case of high speed operation.
240 seg / com driver for stn lcd preliminary spec. ver. 1.0 s 6b 0796 22 table 9 (continued) segment m ode 2 (v ss =v 5 =0v, v dd =+3.0v to +4.5v, v 0 =+15 to +32v, ta=-20~85 c) parameter symbol conditions min. typ. max. unit shift clock period *1 t wck t r , t f 10 ns 66 ns shift clock ?h? pulse width t wckh 23 ns shift clock ?l? pulse width t wckl 23 ns data setup time t ds 15 ns data hold time t dh 23 ns latch pulse ?h? pulse width t wlph 30 ns shift clock rise to latch pulse rise time t ld 0 ns shift clock fall to latch pulse fall time t sl 50 ns latch pulse rise to shift clock rise time t ls 30 ns latch pulse fall to shift clock fall time t lh 30 ns input signal rise time *2 t r 50 ns input signal fall time *2 t f 50 ns enable setup time t s 15 ns dispoffb removal time t sd 100 ns dispoffb ?l? pulse width t wdl 1.2 us output delay time (1) t d c l =15pf 41 ns output delay time (2) t pd1, t pd2 c l =15pf 1.2 us output delay time (3) t pd3 c l =15pf 1.2 us notes: *1 take the cascade connection into consideration. *2 (t wck ? t wckh ? t wckl ) / 2 is maximum in the case of high speed operation.
s 6b 0796 preliminary spec. ver. 1.0 240 seg / com driver for stn lcd 23 table 9 (continued) segment m ode 3 (v ss =v 5 =0v, v dd =+2.4v to +3.0, v 0 =+15 to +32v, ta=-20~85 c) parameter symbol conditions min. typ. max. unit shift clock period *1 t wck t r , t f 10 ns 82 ns shift clock ?h? pulse width t wckh 28 ns shift clock ?l? pulse width t wckl 28 ns data setup time t ds 20 ns data hold time t dh 23 ns latch pulse ?h? pulse width t wlph 30 ns shift clock rise to latch pulse rise time t ld 0 ns shift clock fall to latch pulse fall time t sl 65 ns latch pulse rise to shift clock rise time t ls 30 ns latch pulse fall to shift clock fall time t lh 30 ns input signal rise time *2 t r 50 ns input signal fall time *2 t f 50 ns enable setup time t s 15 ns dispoffb removal time t sd 100 ns dispoffb ?l? pulse width t wdl 1.2 us output delay time (1) t d c l =15pf 57 ns output delay time (2) t pd1, t pd2 c l =15pf 1.2 us output delay time (3) t pd3 c l =15pf 1.2 us notes: *1 take the cascade connection into consideration. *2 (t wck ? t wckh ? t wckl ) / 2 is maximum in the case of high speed operation.
240 seg / com driver for stn lcd preliminary spec. ver. 1.0 s 6b 0796 24 timing c haracteristics of segment m ode (figure 3) t wlph t sl t ld t r t f t ls t lh t wckh t wckl t dh t ds t wck t wdl last data top data t sd lp xck di 0 - di 7 dispoffb t d n ( *) 1 2 t s (*) n : 4 - bit parallel mode 60 8 - bit parallel mode 30 lp xck ei eo
s 6b 0796 preliminary spec. ver. 1.0 240 seg / com driver for stn lcd 25 figure 3 . (continued) fr lp dispoffb y 1 ~y 240 t pd1 t pd2 t pd3 [l/r="l"]
240 seg / com driver for stn lcd preliminary spec. ver. 1.0 s 6b 0796 26 common mode ac character i stics (table 10) common m ode (v ss =v 5 =0v, v dd =+2.4v to +4.5v, v 0 =+15 to +32v, ta=-20~85 c) parameter symbol condition min. typ. max. unit shift clock period t wlp t r , t f 20ns 250 ns v dd =+5.0v 10% 15 ns shift clock ?h? pulse width t wlph v dd =+2.5v~+4.5v 30 ns data setup time t su 30 ns data hold time t h 50 ns input signal rise time t r 50 ns input signal fall time t f 50 ns dispoffb removal time t sd 100 ns dispoffb ?l? pulse width t wdl 1.2 us output delay time (1) t dl cl=15pf 200 ns output delay time (2) t pd1 ,t pd2 cl=15pf 1.2 us output delay time (3) t pd3 cl=15pf 1.2 us timing c haracteristics of common m ode (figure 4) t wlp t r t f t wlph t su t h t d l t wd l t sd lp eio 2 (di 7 ) eio 1 dispoffb
s 6b 0796 preliminary spec. ver. 1.0 240 seg / com driver for stn lcd 27 figure 4 . (continued) t pd1 t pd2 t pd3 fr lp dispoffb y 1 ~ y 240 [l/r="l"]
240 seg / com driver for stn lcd preliminary spec. ver. 1.0 s 6b 0796 28 precaution . precaution when connecting or disconnecting the power this lsi has a high-voltage lc driver, so it may be permanently damaged by a high current which may flow if a voltage is supplied to the lc driver power supply while the logic system power supply is floating. the detail is as follows. . when connecting the power supply, connect the lc drive power after connecting the logic system power. furthermore, when disconnecting the power, disconnect the logic system power after disconnecting the lc driver power. . we recommend you connecting the serial resistor (50~100 w ) or fuse to the lc drive power v 0 of the system as a current limiter. and set up the suitable of the resistor in consideration of lc display grade. and when connecting the logic power supply, the logic condition of this lsi inside is insecurity. therefore connect the lc driver power supply after resetting logic condition of this lsi inside on dispoffb function. after that, cancel the dispoffb function after the lc driver power supply has become stable. furthermore, when disconnecting the power, set the lc drive output pins to level v 5 on dispoffb function. after that, disconnect the logic system power after disconnecting the lc drive power. when connecting the power supply, show the following recommend sequence. v dd dispoffb v 0 v dd v ss v ss v dd v 0 v ss figure 5 .
s 6b 0796 preliminary spec. ver. 1.0 240 seg / com driver for stn lcd 29 connection examples of plural segment drivers eio 2 eio 1 x c k l p m d f r - d i o 7 l/r y240 y1 d i o 0 eio 2 eio 1 x c k l p m d f r - d i o 7 l/r y240 y1 d i o 0 eio 2 eio 1 x c k l p m d f r - d i o 7 l/r y240 y1 d i o 0 top data last data xck lp md fr dio 0 - dio 7 vss 8 eio 1 eio 2 x c k l p m d f r - d i o 7 l/r y1 y240 d i o 0 eio 1 eio 2 x c k l p m d f r - d i o 7 l/r y1 y240 d i o 0 eio 1 eio 2 x c k l p m d f r - d i o 7 l/r y1 y240 d i o 0 top data last data xck lp md fr vdd 8 vss (a) case of l/r = "l" (b) case of l/r = "h" dio 0 - dio 7 figure 6 .
240 seg / com driver for stn lcd preliminary spec. ver. 1.0 s 6b 0796 30 timing chart of 4-device casecade connection of segment drivers n 1 2 n 1 2 n 1 2 n 1 2 n 1 2 fr lp xck di 0 -di 7 ei (device a) eo (device a) eo (device b) eo (device c) device a device b device c device d top data last data (*) (*) n:4-bit parallel mode 60 8-bit parallel mode 30 low figure 7 .
s 6b 0796 preliminary spec. ver. 1.0 240 seg / com driver for stn lcd 31 connection examples of plural common drivers eio 2 eio 1 l p m d f r d i 7 l/r y240 y1 d i s p o f f b first last lp vss fr dispoffb vss di vss (vdd) eio 2 eio 1 l p m d f r d i 7 l/r y240 y1 d i s p o f f b eio 2 eio 1 l p m d f r d i 7 l/r y240 y1 d i s p o f f b eio 1 eio 2 l p m d f r d i 7 l/r y1 y240 d i s p o f f b first last lp vss fr dispoffb vdd di vss (vdd) eio 1 eio 2 l p m d f r d i 7 l/r y1 y240 d i s p o f f b eio 1 eio 2 l p m d f r d i 7 l/r y1 y240 d i s p o f f b (a) single mode(shifting toward left) (b) single mode(shifting toward right) figure 8 .
240 seg / com driver for stn lcd preliminary spec. ver. 1.0 s 6b 0796 32 eio 2 eio 1 l p m d f r d i 7 l/r y240 y1 d i s p o f f b first1 lp vss fr dispoffb vss di1 vss (vdd) eio 2 eio 1 l p m d f r d i 7 l/r y240 y1 d i s p o f f b y121 y120 eio 2 eio 1 l p m d f r d i 7 l/r y240 y1 d i s p o f f b eio 1 eio 2 l p m d f r d i 7 l/r y1 y240 d i s p o f f b first1 last2 lp vss fr dispoffb vdd di1 vss (vdd) eio 1 eio 2 l p m d f r d i 7 l/r y1 y240 d i s p o f f b y120 y121 eio 1 eio 2 l p m d f r d i 7 l/r y1 y240 d i s p o f f b vdd di2 last1 first2 last2 vdd di2 last1 first2 (c) dual mode(shifting toward left) (d) dual mode(shifting toward right) figure 9 .

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